1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device comprised of static type memory cells each including, as a load, two parallel circuits comprised of a Schottky barrier diode (SBD) and resistor.
2. Description of the Prior Art
A static type memory cell usually comprised of a pair transistors formed as a flip-flop and of loads connected to the transistors. The memory cell is driven by a word line and a bit line. The word line is driven by a word decoder driver and the bit line is driven by a bit current supplying circuit (explained in detail hereinafter).
The loads to be connected to the transistors usually comprise a resistor. In recent years, however, loads have often been constructed in a form of SBD's and resistors in parallel circuits. Such loads have the advantage of enabling a high degree of speed in the read/write operation in the memory. The reason for this is well known.
In the prior art, however, static type memory cells containing SBD's, suffer from problems arising from the variation in forward voltage V.sub.F of the SBD's due to the manufacturing process, i.e., arising from the inability to maintain V.sub.F strictly at a predetermined value. The first problem is that a large write margin is required to prevent an erroneous write operation. The second is that an insufficient write current must be compensated.